1. Field of the Invention
The present invention relates to the field of display, and in particular to a high resolution demultiplexer (demux) driver circuit.
2. The Related Arts
The panel display devices, such as, liquid crystal display (LCD) and organic light-emitting diode (OLED) display, comprise a plurality of pixels arranged in an array. Each pixel usually comprises three sub-pixels of red, green and blue respectively. Each sub-pixel is controlled by a gate line and a data line. The gate line is to control the sub-pixel for conduction state, i.e., ON and OFF. The data line is to apply different data voltages to the sub-pixel so that the sub-pixel displays different grayscale to achieve full color display.
As the recent development of high pixel per inch (PPI) panel, more and more panels of higher resolution consume more power due to heavier load and higher frequency. One of the major power consumption comes from the design of the demultiplexer (demux). For high resolution design, because the charging time for demux becomes short, the demux changes from 1-to-many to 1-to-2. For example, for small-size panel with resolution as high as 4K, the 1-to-2 demux is used. Because the PPI is high enough so that a power-saving mode can be activated to cut the resolution to half for the signal line in the Y-direction to reduce the power consumption.
Refer to FIG. 1. FIG. 1 is a schematic view showing the circuit of a known 1-to-2 demux. Based on the known RGB display panel, the circuit of the display panel is of a regular specification, and row scan lines G1, G2, . . . , are connected respectively to sub-pixels of corresponding rows, and data lines D1, D2, . . . , are connected respectively to sub-pixels of corresponding columns. Each sub-pixel is connected through a corresponding thin film transistor (TFT) corresponding to the row of which the sub-pixel belongs to and the data line corresponding to the row of which the sub-pixel belongs to and the data line corresponding to the column of which the sub-pixel belongs to. The circuit of the demux comprises a plurality of multiplexer (mux) modules. Take the mux module 10 as example. The mux module 10 comprises two TFTs, with the gates connected respectively to a first shunt control signal demux1 and a second shunt control signal demux2, the sources connected to the same data signal Data1 (+), i.e., a voltage of the same polarity from the data integrated circuit (IC) signal, and the drains connected respectively to data line D1 and data line D3.
Refer to FIG. 2 and FIG. 3. FIG. 2 is a schematic view showing the power-saving mode signal and circuit of a known 1-to-2 demux circuit, and FIG. 3 a schematic view showing the driving signal in power-saving mode signal of a known 1-to-2 demux circuit. When the power-saving mode is activated, two pixels are considered as a smallest unit (each pixel comprising three R/G/B sub-pixels in FIG. 2). Therefore, the resolution in Y direction is cut to half, as shown FIG. 2, wherein two dash line boxes become the smallest unit, and the levels for the R/G/B color are L240/L127/L30 respectively. The level indicates the index standard for the pixel luminance intensity. In general, for 8-bit RGB color space, 256 levels are used respectively to represent red, green and blue. That is, each color ranges between [0, 255]. In FIG. 2, the levels for R/G/B are 240, 127 and 30 respectively. At this point, the related signals are shown in FIG. 3, comprising: G1 (gate signal), Data1 (+), Data2 (−), Data3 (+), first shunt control signal Demux1 and second shunt control signal Demux2. Although the adjacent same color (with two pixels as the smallest unit) has the same level, the data signal still requires changes in voltage difference. Hence, a large amount of power consumption still incurs.